Before electronic circuit chips are packaged, they are conventionally tested to retrieve information about their performance levels. A performance criterion, for example, are voltage level discrepancies within the tested chip. The continuing development of circuit chips results in an ever decreasing voltage level at which the circuit chips operate and have to be tested. The recognition of voltage level discrepancies at ever decreasing operational voltage levels requires more precise inducing and deriving of test signals during the chip testing. For a cost effective chip fabrication it is at the same time desirable to have a probe apparatus capable of compensating for a broader bandwidth of physical and dimensional tolerances of the chip terminals accessed during the chip testing. On the other hand, the chip testing has to be performed with shortest possible testing times, leaving little time for establishing sufficient contacting quality between the probes and the chip terminals.
The contacting quality is mainly defined by a resistance in an interface between probe tip and chip terminal. To reduce the interface resistance, probes and/or the probe apparatus are commonly configured to scrub slightly along the terminal surface and thereby remove thin insulating oxidation layers. With decreasing sizes of the chip terminals and decreasing terminal surface radii in case of solder bumps or solder balls, scrubbing distances may become shorter. As a result, the removal of oxide layers becomes more difficult to accomplish.
Therefore, there exists a need for a probe apparatus capable of recognizing resistance discrepancies in the probe/terminal interfaces and for correspondingly adjusting a voltage level of a consecutive operational signal applied onto or derived from the chip terminal during the actual chip testing. The present invention addresses this need.